Robust SEU Mitigation With Stratix III FPGAs
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چکیده
The benefits of FPGAs over ASICs become ever more compelling as rapid-process technology scaling and innovation provide ever-greater speed, density, and power improvements. However, along with technology scaling come other effects that previously could be ignored. One of the accompanying effects is increased susceptibility to soft errors caused by single event upsets (SEUs). Although through careful IC design the soft error rate per bit decreases at 65 nm, each process technology generation offers twice the logic density, bringing with it a corresponding doubling in the number of configuration RAM (CRAM) bits.
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تاریخ انتشار 1998